In integrated circuit (IC) devices, resistive random access memory (RRAM) is an emerging technology for next generation non-volatile memory devices. RRAM is a memory structure including an array of RRAM cells each of which stores a bit of data using resistance values, rather than electronic charge. Particularly, each RRAM cell includes a resistive material layer, the resistance of which can be adjusted to represent logic “0” or logic “1.” There are various architectures to configure an array of RRAM cells. For example, a cross-point architecture include only a RRAM in each cell configured between crossed a word line and a bit line. The cross-point architecture has a high packing density but has a sneak path issue, which causes a fault read during operation. A complementary resistive switches (CRS) structure was recently suggested to solve the sneak path problem of larger passive memory arrays. CRS cells consist of an anti-serial setup of two bipolar resistive switching cells. In the CRS approach, the two storing states are pairs of high and low resistance states so that the overall resistance is always higher, allowing for larger passive cross-point arrays. However, the CRS architecture needs more material layers, therefore more processing steps and more fabrication cost.
Accordingly, it would be desirable to provide an improved RRAM structure and method of manufacturing thereof absent the disadvantages discussed above.